View DS3803_307587.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS3803 1024k Flexible NV SRAM SIMM
www.dalsemi.com
FEATURES
Flexibly organized as 32k x 32, 64k x 16 or 128k x 8bits 10 years minimum data retention in the absence of external power Nonvolatile circuitry transparent to and independent from host system Automatic write protection circuitry safeguards against data loss Separate control and data signals for each SRAM allow byte, word or doubleword access Fast access time of 70 ns Full VCC 10% operating range Employs popular JEDEC standard 72-position SIMM connector Extremely thin design built using TSOPpackage IC components
PIN ASSIGNMENT
1
256K SRAM 256K SRAM 256K SRAM 256K SRAM DS3803 72-Pin SIMM
PIN DESCRIPTION
A0 - A14 D0A - D7A D0B - D7B D0C - D7C D0D - D7D CEA - CED WEA - WED OEA - OED VCC GND NC Address Inputs Data Inputs/Outputs, Byte A Data Inputs/Outputs, Byte B Data Inputs/Outputs, Byte C Data Inputs/Outputs, Byte D Chip Enable Inputs Write Enable Inputs Output Enable Inputs +5V Power Supply Ground No Connect
72
DESCRIPTION
The DS3803 is a self-contained, 1,048,576-bit, nonvolatile static RAM which can be flexibly organized as 32k x 32, 64k x 16 or 128k x 8. Built using four 32k x 8 SRAMs, four nonvolatile control ICs and four lithium batteries, this nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS3803 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry. 1 of 10 112299
DS3803
READ MODE
The DS3803 executes a read cycle whenever WE (Write enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 A14) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than tACC .
WRITE MODE
The DS3803 executes a write cycle whenever both WE and CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS3803 provides full functional capability for VCC greater than 4.5 volts and write-protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write-protects itself, all inputs become don't care, and all outputs become high impedance. As VCC falls below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the RAMs to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuits connect external VCC to the RAMs and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. The DS3803 checks battery status to warn of potential data loss. Each time that VCC power is restored to the DS3803, the battery voltages are checked with precision comparators. If both batteries providing backup power to a particular SRAM are less than 2.0 volts, the second memory access to that SRAM is inhibited. Battery status for each SRAM can therefore be determined by a three-step process. First, a read cycle is performed to any location within that SRAM in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If a subsequent read cycle fails to verify the written data, then battery voltage for that SRAM is less than 2.0V and data is in danger of being lost. The DS3803 also provides battery redundancy. In many applications data integrity is paramount. The DS3803 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user.
2 of 10
DS3803
PIN DESCRIPTION Table 1
PIN SIGNAL PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VCC D0A D1A D2A D3A D4A D5A D6A D7A NC
CEA OEA WEA
SIGNAL NAME D2B D3B D4B D5B D6B D7B NC
CEB CEB WEB
PIN SIGNAL NAME 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 D5C D6C D7C NC
CEC OEC WEC
PIN 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
SIGNAL NAME NC
CED OED WED
PIN 61 62 63 64 65 66 67 68 69 70 71 72 A9
SIGNAL NAME
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A10 A11 A12 A13 A14 NC NC NC NC NC GND
GND VCC A0 A1 A2 A3 A4 A5 A6 A7 A8
D0D D1D D2D D3D D4D D5D D6D D7D
D0C D1C D2C D3C D4C
D0B D1B
3 of 10
DS3803
BLOCK DIAGRAM Figure 1
4 of 10
DS3803
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature -0.3V to +7.0V 0C to 70C -40C to +85C
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Logic 1 input Voltage Logic 0 input Voltage SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 TYP 5.0 MAX 5.5 VCC+0.3 +0.8
(TA = 0C to 70C)
UNITS V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current Output Leakage Current Operating Current SYMBOL IIL ILO ICCO
(TA = 0C to 70C; VCC = 5V 10%)
MIN -4 -1 TYP MAX +4 +1 300 UNITS A A mA
TEST CONDITION 0V VIN VCC 0V VIN VCC, all CE = VIH min cycle, duty=100% all CE = VIL, II/O = 0, VIN = VIH or VIL all CE = VIH VOH = 2.4V VOL = 0.4V
Standby Current Output High Current Output Low Current
ICCS IOH IOL
20 -1.0 2.1
mA mA mA
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN CI/O MIN TYP MAX 8 10 pF pF
(TA = 25C)
UNITS NOTES
5 of 10
DS3803
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Access Time OE to Output Valid
CE to Output Valid OE or CE to Output Active
(TA = 0C to 70C; VCC = 5V 10%)
TYP MAX 70 35 70 5 25 5 UNITS ns ns ns ns ns ns ns ns ns ns ns 25 ns ns ns ns 5 5 NOTES
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 70
Deselection to Output High Z Output Hold after Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time
WE Active to Output High Z WE Inactive to Output Active
70 55 0 5 15 5 30 0 10
3 11 12 5 5 4 11 12
Data Setup Time Data Hold Time
TIMING DIAGRAM: READ CYCLE
6 of 10
DS3803
TIMING DIAGRAM: WRITE CYCLE 1 ( WE Controlled)
TIMING DIAGRAM: WRITE CYCLE 2 ( CE Controlled)
7 of 10
DS3803
TIMING DIAGRAM: POWER-DOWN AND POWER-UP
POWER-DOWN AND POWER-UP TIMING
PARAMETER VCC Fail Detect to
CE and WE Inactive
SYMBOL tPD
MIN
TYP
MAX 1.5
UNITS s
NOTES
VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to
CE and WE Inactive
tF tR tPU
300 300 2
s s ms
VCC Valid to End of Write Protection
tREC
125
ms
(TA = 25C)
PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9
WARNING
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high throughout read cycle. 2.
OE = VIH or VIL. If state. OE
= V IH during write cycle, the output buffers remain in a high impedance 8 of 10
DS3803
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS3803 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 11. tWR1, tDH1 are measured from WE going high. 12. tWR2, tDH2 are measured from CE going high.
DC TEST CONDITIONS
Outputs Open Cycle = 200 ns All Voltages are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL gate Input Pulse Levels: 0 - 3.0 V Timing Measurements Reference Levels: Input - 1.5V Output - 1.5V Input Pulse Rise and Fall Times: 5 ns
9 of 10
DS3803
DS3803 72-PIN SIMM MODULE
DIM A B C D E F G H I J K L M N O P
72-PIN MIN MAX 4.245 4.255 3.979 3.989 0.845 0.855 0.395 0.405 0.245 0.255 0.050 BASIC 0.075 0.085 0.245 0.255 1.750 BASIC 0.120 0.130 2.120 2.130 2.245 2.255 0.057 0.067 0.173 0.110 0.047 0.054
10 of 10

▲Up To Search▲

Price & Availability of DS3803

	To Download DS3803 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .